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What is the PDP-11 instruction set?

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The instruction space of the PDP-11 became once designed in direction of a ravishing,
accepted, symmetric instruction space. It’ll also be outdated as a
register-based fully mostly, stack-based fully mostly, or memory-based fully mostly machine, relying
on the programmer’s preferences. Interrupt responsiveness is
furthermore critical, supported with a pair of interrupt ranges for
loyal-time computing moreover taking into memoir a separate interrupt
handler for every instrument that generates interrupts.

Word length is 16 bits with the leftmost, most critical bit
(MSB) being bit 15. There are eight accepted registers of 16 bits
every. Register 7 is the program counter (PC) and, by conference,
Register 6 is the stack pointer (SP). There is furthermore a Processor
Popularity Register/Word (PSW) which indicates the 4 situation code
bits (N, Z, V, C), the Hint Entice bit, processor interrupt
priority, and 4 bits for contemporary and outdated running modes.
Addressing on the -11 is linear from memory address 0 thru
177777. Reminiscence management permits entry to physical memory with
addresses of as much as 22 bits (17777777). All I/O devices,
registers and masses others are addressed as in the occasion that they have been segment of memory.
These live in the 4KW of reserved memory house at the pinnacle of the
addressing fluctuate. Additionally, on most implementations of the
PDP-11 structure, the processor’s registers are memory-mapped
to the fluctuate 17777700-17777717 (there are a spacious different of support watch over registers
beyond simply the accepted registers, the specifics vary between
implementations). Thus Register 2 (R2) has an address of
17777702. All discover memory addresses are even, excluding for registers.
In byte operations, a ultimate address specifies the least-critical
byte and an uncommon address specifies the most-critical byte.
Specifying an uncommon byte in a discover operation will return an uncommon
address entice. Reminiscence addresses from 0 to 400 octal are reserved
for diversified exception traps such as timeouts, reserved
directions, parity, and masses others., and instrument interrupts.

Addressing for the Single Operand, Double Operand and
Jump directions is finished through six bits:

                          _ _ _ _ _ _
                         |x|x|x|_|_|_|
                         |Mode |Reg  |

the set the modes are as follows: (Reg = Register, Def = Deferred)

     Mode 0  Reg           Divulge addressing of the register
     Mode 1  Reg Def       Contents of Reg is the address
     Mode 2  AutoIncr      Contents of Reg is the address, then Reg incremented
     Mode 3  AutoIncrDef   Content of Reg is addr of addr, then Reg Incremented
     Mode 4  AutoDecr      Reg is decremented then contents is address
     Mode 5  AutoDecrDef   Reg is decremented then contents is addr of addr
     Mode 6  Index         Contents of Reg + Following discover is address
     Mode 7  IndexDef      Contents of Reg + Following discover is addr of addr

Expose that the true-most little bit of the mode is an indirection bit.

Even supposing no longer particular cases, when going thru R7 (aka the PC), about a of
these operations are known as diversified things:

                          _ _ _ _ _ _
                         |x|x|x|1|1|1|
                         |Mode |  R7 |

     Mode 2  Instantaneous     Operand follows the instruction
     Mode 3  Absolute      Address of Operand follows the instruction
     Mode 6  Relative      Instr address+4+Next discover is Address
     Mode 7  RelativeDef   Instr address+4+Next discover is Address of address

Mainstream directions are damaged into Single operand and Double
operand directions, which in turn could even be discover or byte directions.

Double Operand Instructions

                      _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
                     |b|i|i|i|s|s|s|s|s|s|d|d|d|d|d|d|
                     | |     |     :     |     :     |
                     | | Op  | Provide    |  Dest     |

Bit 15, b, on the total selects between discover-sized (b=0) and
byte-sized (b=1) operands. Within the desk below, the mnemonics and
names are given in the repeat b=0/b=1.

The double operand directions are:

b 000 ssssss dddddd
Non-double-operand directions.
b 001 ssssss dddddd — MOV/MOVB Switch Word/Byte
Strikes a tag from offer to proceed narrate.
b 010 ssssss dddddd — CMP/CMPB Evaluation Word/Byte
Compares values by subtracting the proceed narrate
from the provision, atmosphere the placement codes, and
then discarding the of the subtraction.
b 011 ssssss dddddd — BIT/BITB Bit Test Word/Byte
Performs somewhat-smart AND of the provision and the
proceed narrate, sets the placement codes, after which
discards the of the AND.
b 100 ssssss dddddd — BIC/BICB Bit Sure Word/Byte
For every bit space in the provision, that bit is cleared
in the proceed narrate. This is finished by taking the
ones-complement of the provision and ANDing it with the
proceed narrate. The outcomes of the AND is saved in the
proceed narrate.
b 101 ssssss dddddd — BIS/BISB Bit Draw Word/Byte
For every bit space in the provision, that bit is space in
the proceed narrate. This is finished by ORing the
offer and proceed narrate, and storing the in the
proceed narrate.
b 110 ssssss dddddd — ADD/SUB Add/Subtract Word
Adds the provision and proceed narrate, storing the outcomes
in the proceed narrate.

Subtracts the provision from the proceed narrate, storing
the ends in the proceed narrate.

Expose that here’s a obvious case for b=1, in that
it would not show cowl that byte-huge operands are
outdated.

b 111 xxxxxx xxxxxx
Arithmetic functions no longer supported by all implementations
of the PDP-11 structure.

Single Operand Instructions

                      _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
                     |b|0|0|0|i|i|i|i|i|i|d|d|d|d|d|d|
                     | |     |     :     |     :     |
                     | |     |Instruction|  Dest     |

Bit 15, b, on the total selects between discover-sized (b=0) and
byte-sized (b=1) operands. Within the desk below, the mnemonics and
names are given in the repeat b=0/b=1. Unless otherwise acknowledged,
the operand is read for the records to operate on, and the is
then written over that records.

The one operand directions are:

b 000 000 011 dddddd — SWAB/BPL Swap Bytes/Division Plus
Swap bytes exchanges the two bytes stumbled on in the
proceed narrate, writing the back to it.

The branch (b=1) is described in the share on
branches, below.

Expose that SWAB is in total somewhat sample from the
fluctuate reserved for branches. This particular
sample is otherwise unused, as it could perchance probably perchance be a
modification of BR, Division Continuously, which has no
evident semantics.

b 000 101 000 dddddd — CLR/CLRB Sure Word/Byte
Sets your entire bits in proceed narrate to zero.
b 000 101 001 dddddd — COM/COMB Complement Word/Byte
Calculates those-complement of the operand,
and stores it. The ones-complement is fashioned by
inverting every bit (0->1, 1->0) independently.
b 000 101 010 dddddd — INC/INCB Increment Word/Byte
Adds one to the proceed narrate.
b 000 101 011 dddddd — DEC/DECB Decrement Word/Byte
Subtracts one from the proceed narrate.
b 000 101 100 dddddd — NEG/NEGB Mumble Word/Byte
Calculates the twos-complement of the operand,
and stores it. The twos-complement is fashioned by
including one to those-complement. The produce is
the identical as subtracting the operand from zero.
b 000 101 101 dddddd — ADC/ADCB Add Raise Word/Byte
Adds the contemporary tag of the carry flag to the
proceed narrate. This is first-price for imposing
arithmetic subroutines with bigger than discover-sized
operands.
b 000 101 110 dddddd — SBC/SBCB Subtract Raise Word/Byte
Subtracts the contemporary tag of the carry flag from
the proceed narrate. This is first-price for imposing
arithmetic subroutines with bigger than discover-sized
operands.
b 000 101 111 dddddd — TST/TSTB Test Word/Byte
Sets the N (unfavorable) and Z (zero) situation codes
based fully totally on the tag of the operand.
b 000 110 000 dddddd — ROR/RORB Rotate Lawful Word/Byte
Rotates the bits of the operand one station to
the true. The real-most bit is placed in the
carry flag, and the carry flag is copied to the
left-most bit (bit 15) of the operand.
b 000 110 001 dddddd — ROL/ROLB Rotate Left Word/Byte
Rotates the bits of the operand one station to
the left. The left-most bit is placed in the
carry flag, and the carry flag is copied to the
real-most bit (bit 0) of the operand.
b 000 110 010 dddddd — ASR/ASRB Arithmetic Shift Lawful Word/Byte
Shifts the bits of the operand one station to
the true. The left-most bit is duplicated. The
produce is to compose a signed division by 2.
b 000 110 011 dddddd — ASL/ASLB Arithmetic Shift Left Word/Byte
Shifts the bits of the operand one station to
the left. The real-most bit is space to zero. The
produce is to compose a signed multiplication by 2.
b 000 110 100 dddddd — MARK/MTPS Sign/Switch To Processor Popularity
MARK is outdated as segment of 1 in every of the subroutine name/
return sequences. The operand is the different of parameters.
Admittedly significantly cryptically, MARK does:

                  SP <

Also, for the instruction to work, the stack deserve to be mapped into I-house.

MTPS is simplest on LSI-11s, and is outdated to transfer a byte to the processor narrate discover. This is wished for the reason that LSI-11 would not reinforce accessing registers through memory addresses.

b 000 110 101 dddddd — MFPI/MFPD Switch From Prev. Instruction/Data
Pushes a discover onto the contemporary R6 stack from the
operand address in the outdated address house, as
indicated in the PSW. On PDP-11s that produce no longer
reinforce separate instruction and records spaces, MFPD
is handled the identical as MFPI.
b 000 110 110 dddddd — MTPI/MTPD Switch To Old Instruction/Data
Pops a discover from the contemporary stack as indicated in
the PSW to the operand address in the outdated
address house, as indicated in the PSW. On
PDP-11s that produce no longer reinforce separate instruction
and records spaces, MTPD is handled the identical as MTPI.
b 000 110 111 dddddd — SXT/MFPS Ticket Lengthen/Switch From Processor Popularity
SXT sets the proceed narrate to zero if the N (unfavorable)
flag is evident, or to all ones if N is space. This
is first-price for imposing arithmetic subroutines
with bigger than discover-sized operands.

MFPS copies the processor narrate byte to the indicated
register. This simplest exists on LSI-11s, and is wished
there as a result of those systems produce no longer reinforce accessing
registers through memory addresses.

Branches

                      _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
                     |b|0|0|0|b|b|b|b|d|d|d|d|d|d|d|d|
                     |  Division Code  |  Vacation narrate  |

The proceed narrate of a branch is +127 to -128 phrases from the discover
following the branch instruction itself. This appears to be like a diminutive bit
uncommon, till you respect the sequence of occasions: the branch
instruction is read from memory and the PC incremented. If the
branch is to be taken, the offset is then added to the contemporary
tag of the PC. For the reason that PC has already been incremented, the
offset is thus relative to the following discover. Expose that every
branch directions are one discover prolonged.

The diversified branches take a look at the values of advise situation
codes, and if the assessments be triumphant, the branch is taken. The
situation codes are N (unfavorable), Z (zero), C (carry), and V
(overflow). Within the desk below, the branch assessments are confirmed as
boolean expressions. `x’ stands for uncommon-OR. `v’ stands
for inclusive-OR.

0 000 000 1dd dddddd
BR: Division Continuously
0 000 001 0dd dddddd
BNE: Division if No longer Equal (Z==0)
0 000 001 1dd dddddd
BEQ: Division if EQual (Z==1)
0 000 010 0dd dddddd
BGE: Division if Higher or Equal (NxV == 0)
0 000 010 1dd dddddd
BLT: Division if Much less Than (NxV == 1)
0 000 011 0dd dddddd
BGT: Division if Higher Than (Zv(NxV) == 0)
0 000 011 1dd dddddd
BLE: Division if Much less or Equal (Zv(NxV) == 1)
1 000 000 0dd dddddd
BPL: Division if PLus (N == 0)
1 000 000 1dd dddddd
BMI: Division if MInus (N == 1)
1 000 001 0dd dddddd
BHI: Division if HIgher (C==0 and Z==0)
1 000 001 1dd dddddd
BLOS: Division if Decrease Or Identical (CvZ == 1)
1 000 010 0dd dddddd
BVC: Division if oVerflow Sure (V == 0)
1 000 010 1dd dddddd
BVS: Division if oVerflow space (V == 1)
1 000 011 0dd dddddd
BCC: Division if Raise Sure (C == 0)


furthermore known as


BHIS: Division if Higher Or Identical
1 000 011 1dd dddddd
BCS: Division if Raise Draw (C == 1)


furthermore known as


BLO: Division if Decrease

Situation Code Operations

                      _ _ _ _ _ _ _ _ _ _:_ _ _:_ _ _
                     |0|0|0|0|0|0|0|0|1|0|1|s|N|Z|V|C|
                     |     O p c o d e     | | Cloak  |

Well-liked opcode 000240x. Draw/Sure corresponding bits reckoning on sense
of bit 04 (space=1, obvious=0). Codes 240 and 260 space/obvious no bits
and are, thus, outdated as NOP. Even supposing advise mnemonic are supplied
for every flag and all flags, any mixture could even very effectively be space or
cleared at a time.

Well-liked mnemonics are:

CLx
Sure x, the set x is N, Z, V, or C
SEx
Draw x, the set x is N, Z, V, or C
CCC
Sure all situation codes
SCC
Draw all situation codes


0 000 000 010 1s0 000
NOP/NOP: No Operation
0 000 000 010 1s0 001
SEC/CLC: Draw/Sure Raise
0 000 000 010 1s0 010
SEV/CLV: Draw/Sure Overflow
0 000 000 010 1s0 100
SEZ/CLZ: Draw/Sure Zero
0 000 000 010 1s1 000
SEN/CLN: Draw/Sure Unfavourable
0 000 000 010 1s1 111
SCC/CCC: Draw/Sure All Situation Codes

Other, Miscellaneous

                      _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
                     |0|0|0|0|1|0|0|s|s|s|d|d|d|d|d|d|
                     |   Opcode    |Stack|Vacation narrate|
0 000 100 sss dddddd — JSR Jump to Subroutine
The loyal sequence of steps taken is:

                  MOV ,-(R6)
                  MOV PC,
                  JMP 

Thus, it saves the contemporary contents of the specified offer
register on the stack, then copies the contemporary program
counter to the simply-saved register, and finally jumps to
the indicated proceed narrate. The fun segment is (as long-established
with the PDP-11) that the PC is a accepted register (R7), and
the utilization of it because the provision ends in:

                  MOV ,-(R6)         ; push return address onto stack
                  MOV PC,PC                    ; no-op
                  JMP       ; soar to proceed narrate
                      _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
                     |0|0|0|0|0|0|0|0|1|0|0|0|0|s|s|s|
                     |          Opcode         |Stack|
0 000 000 010 000 sss — RTS ReTurn from Subroutine
Undoes the outcomes of a JSR. For predictable
outcomes, it is urged that the identical register could even unexcited
be outdated as became once named in the corresponding JSR
instruction.

The loyal operations sharp are:

                  MOV ,PC
                  MOV (R6)+,

This is the reverse of JSR. Obviously, the finesse
here too is that you just’ll be in a space to employ the PC, to get what
of us in total assign in options a CALL/RETURN aim. In that
case, the main MOV is a no-op and the second pops the
return address off of the stack and into the program counter.

Why is it done like this then? Effectively, assign in options this
example:

                  ...
                       JSR   R0,FOO
                       .WORD A
                       .WORD B
                       MOV   R1,C
                  ...

                  FOO: MOV   @(R0)+,R1
                       ADD   @(R0)+,R1
                       RTS   R0

This impact of in-line parameter passing is outdated widely
in the PDP-8 and PDP-10, as an illustration. Also, the
FORTRAN runtime map on the PDP-11 does it this
device. (It’s miles somewhat easy to write down a compiler who
generates the type of calling sequence, after which have a
library of functions which quiz this calling
conference.)

                      _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
                     |0|0|0|0|0|0|0|0|0|1|d|d|d|d|d|d|
                     |       Opcode      |Vacation narrate|
0 000 000 001 ddd ddd — JMP JuMP
Hundreds the proceed narrate address into the PC, thus
effecting an unconditional soar. Expose that a entice will
occur on some systems if an uncommon address is specified.
On others, the proceed narrate is silently rounded down to
the next-decrease even address (i.e., the true-most bit is
neglected).
                      _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
                     |0|0|0|0|0|0|0|0|0|0|0|0|0|i|i|i|
                     | |     |     |     |     | Op  |
0 000 000 000 000 000 — HALT Halts the machine

Ceases I/O, and affords support watch over to the console. Operator
intervention is required to continue or restart the
map.

0 000 000 000 000 001 — WAIT WAIT for interrupt

0 000 000 000 000 010 — RTI ReTurn from Interrupt

0 000 000 000 000 100 — BPT BreakPoint Entice

0 000 000 000 000 101 — RESET Initializes the map

The next opcode ranges are all unused (the utilization of three bits per digit):

00 00 07 .. 00 00 77

00 02 10 .. 00 02 27

00 70 00 .. 00 77 77

07 50 40 .. 07 67 77

10 64 00 .. 10 64 77

10 67 00 .. 10 77 77

Other arithmetic and floating level directions have been added to
the predominant space over time, but those listed above impact the
core PDP-11 instruction space.

There is a comparability of PDP-11 and 80×86 floating level codecs
on hand at:
ftp://ftp.dbit.com/pub/pdp11/recordsdata/fpp.txt


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